1. Fields of the Invention
The preset invention relates to a chip package structure, especially to a die with a plurality of bonding pads. Each bonding pad includes a conductive wire extended outward and a solder point. The die is electrically connected and assembled with a substrate by each conductive wire and each solder point.
2. Descriptions of Related Art
Along with development of semiconductor manufacturing processes, there are various manufacturing processes and structures of the chip package, as shown in U.S. Pat. Nos. 6,239,488, 5,990,546, 6,143,991, 6,075,712, and 6,114,754. In early days, a TAB (Tape automated bonding) technique is developed and used. But outer lead portions extended from the pad-mounting surface of the plurality of bonding die pads causes the increased package size and this is not satisfied with the requirement of high density. In recent years, a CSP (chip scale package) technique is developed and used. A plurality of various manufacturing processes and structure have also been derived. Although CSP solves the problem of larger package size caused by TAB, it still has problems of complicated manufacturing processes, low yield rate of the products and increased manufacturing cost. Refer to claim 1, claim 6, FIG. 1 to FIG. 7 and FIG. 14 to FIG. 19 in U.S. Pat. No. 6,239,488, conductive bodies 3 are directly formed on a pad-mounting surface 10 and there is no dielectric layer between the conductive bodies 3 and the pad-mounting surface 10. This has negative effect on the insulation effect between the conductive bodies 3 and other bonding pads and the product yield rate is reduced. Moreover, according to the processes and structure revealed by this prior art, the step that produces the conductive body 3 can't be repeated so that the conductive body 3 is with only single-layer structure, not double-layer structure. Thus the space on the pad-mounting surface 10 for establishing the required electrical connection is also reduced.
However, according to the structure and manufacturing processes mentioned in U.S. Pat. No. 6,239,488, the step of forming the conductive body 3 is unable to be repeated so that the conductive body 3 only has a single-layer structure. Thus the use efficiency of the wiring space on the pad-mounting surface 10 of a die is further reduced. Moreover, this prior art also restricts the formation method of the conductive body 3 in the chip package structure and the technique revealed by the steps in the claim 1 intends to make greater difference than other prior techniques disclosed in U.S. Pat. Nos. 5,990,546, 6,143,991, 6,075,712, and 6,114,754. However, the not only the scope of the claim is limited, but the formation and the structure of the conductive body 3 are complicated that lead to increased manufacturing cost. Thus there is a need to improve the chip package structure and the related manufacturing processes.